An Analog-assisted Fast-transient Digital LDO with a Charge-pump-based Fine Loop Achieving 0.14-mV Output Voltage Ripples

This paper presents a digital low dropout (DLDO) regulator, which has very small steady-state voltage ripples (V_RIPP) of < 140 μV and a minimum dropout voltage of 20 mV, for driving both noise-sensitive analog and power-efficient digital load circuits in system-on-chip devices. To eliminate V_RIPP, a steady-state control based on a voltage-to-interval converter and a charge pump is proposed. To achieve a fast transient response, a dual-edge-triggered shift registers (DTSR) is used in the coarse loop. In addition, an analog-assisted (AA) loop is proposed to significantly mitigate the voltage undershoot in response to a load current (I_LOAD) step. The DLDO was designed and fabricated in a 180-nm CMOS process with an active area of 0.253 mm². The simulated results demonstrate that the proposed DLDO achieves a line regulation of 8 mV/V and a load regulation of 0.081 mV/mA while driving a maximum I_LOAD of 75 mA with a peak current efficiency of 99.93 %.