An Area-Efficient, DC-Coupled VCO-Based CT ΔΣM with Input-TR-DAC for Neural Recording

This paper presents a neural recording integrated circuit (IC) with a DC-coupled VCO-based continuous-time ΔΣ modulator with a novel input transistor ΔΣ digital-to-analog converter (DAC) technique. The input transistor operating as a transconductor is implemented in the form of a transistor DAC (TR-DAC) consisting of multiple transistors, which enables the ΔΣ operation according to the output digital code. Notably, this topology isolates the input from the feedback loop, resulting in exceptionally high input impedance. Furthermore, the input transistor itself functions as a ΔΣ DAC, eliminating the need for additional passive or active DAC components. Consequently, the proposed design significantly reduces area consumption, enabling its application to future scalable brain-machine-interface (BMI) systems. The proposed IC designed in a 0.18-μm CMOS process consumes only 4.7 μW with a bandwidth of 5.12 kHz. Thanks to its DC-coupling characteristics and small input parasitic capacitance, the design achieves a high input impedance of 1.26 GΩ. Furthermore, the chip occupies a compact area of 0.054 mm² per channel, while the input TR-DAC used as a ΔΣ DAC occupies only 0.008